OM-USB-3103美国OMEGA

　　The new OM-USB-3101, OM-USB-3103, and OM-USB-3105 are voltage output USB 2.0 full-speed modules. Each module provides 4, 8, or 16 voltage outputs. All modules provide synchronous and concurrent voltage s. All OM-USB-3100 Series modules provide eight digital I/O lines and one 32-bit event counter and are powered by the 5V USB supply from the computer.

　　Analog Output

　　All OM-USB-3100 Series modules provide either 4, 8, or 16 channels of 16-bit analog output. Each channel is software-able for either a bipolar voltage output range of ±10 V or unipolar range of 0 to 10V. Channel outputs can be d individually or simultaneously.

　　Software

　　The OM-USB-3100 Series modules ship with an impressive array of software including the new TracerDAQ?, a full-featured, out-of-the-box data logging, viewing, and analysis application. Driver support and detailed example programs are included for Universal Library programming libraries for Microsoft? Visual Studio? programming languages, and other languages, including DASYLab?, and ULx for NI LabVIEW? (comprehensive library of Vls and example programs compatible with 32-bit and 64-bit LabVIEW v8.5 through 2012) and InstaCalTM installation, calibration and test utility-powerful solutions for programmers and nonprogrammers alike. These modules operate under Microsoft Windows? XP (32-bit only) and VISTA/7 AND 8 (32-bit and 64-bit) operating systems.

　　Synchronous DAC s

　　All OM-USB-3100 Series modules have a synchronous DAC load connection pin (SYNCLD) that simultaneously s DAC outputs on multiple devices. You can configure this with software as an input (slave mode) or as an output (master mode). In slave mode, the SYNCLD pin receives the D/A LOAD signal from an external source. When the SYNCLD pin receives the trigger signal, the analog outputs are d simultaneously. In master mode, the internal D/A LOAD signal is sent to the SYNCLD pin. You can then synchronize with a second device of the same type and simultaneously the DAC outputs on each device. On power up and reset, the SYNCLD pin is set to slave mode (input).

　　Digital I/O

　　All OM-USB-3100 Series modules have eight bidirectional digital I/O connections. The digital DIO lines can be independently programmed for input or output. All digital pins are floating by default. A screw terminal connection is provided to configure for pull-up (5V) or pull-down (0V).

　　Counter Input

　　Each OM-USB-3100 Series module has a 32-bit event counter for counting TTL pulses. The counter increments when the TTL levels transition from low to high. The counter accepts frequency inputs of up to 1 MHz.

　　SPECIFICATIONS

　　ANALOG VOLTAGE OUTPUT

　　D/A Converter: DAC8554

　　Number of Channels:

　　OM-USB-3101: 4

　　OM-USB-3103: 8

　　OM-USB-3105: 16

　　Output Ranges (Software-able):

　　Calibrated: ±10V, 0V to 10V

　　Uncalibrated: ±10.2V, -0.04V to 10.08V

　　Resolution: 16 bits

　　Absolute Accuracy (Calibrated Output):

　　±10V: ±4.0 LSB

　　0 to 10V: ±22.0 LSB

　　Relative Accuracy (±LSB):

　　±10V, 0 to 10V: 4.0 typical, 12.0 maximum

　　Output Transient (±10V to 0 to 10V or 0 to 10V to ±10V):

　　Range ion: The output voltage level defaults to 0V when the output voltage range is reconfigured, the host computer is reset, shut down, or suspended, or a reset command is issued to the device.

　　Duration: 5 μs typical

　　Amplitude: 5V p-p typical

　　Host Computer is Reset, Powered On, Suspended, or a Reset Command is Issued to Device: The duration of this output transient is depends highly on the enumeration process of the host computer. Typically, the output is stable after two seconds.

　　Duration: 2 s typical

　　Amplitude: 2V p-p typical

　　Initial Power On:

　　Duration: 50 ms typical

　　Amplitude: 5V peak typical

　　Differential Nonlinearity: The maximum differential nonlinearity specification applies to the entire operating temperature range. This specification also accounts for the maximum errors due to the software calibration algorithm (in calibrated mode only) and the DAC8554 nonlinearities)

　　Calibrated: ±1.25 LSB typical, -2 LSB to 1 LSB maximum

　　Uncalibrated: ±0.25 LSB typical, ±1 LSB maximum

　　Output Current (VOUTx Pins): ±3.5 mA typical

　　Output Short-Circuit Protection (VOUTx Connected to AGND): Indefinite

　　Output Coupling: DC

　　Power On and Reset State:

　　DACs Cleared to Zero-Scale: 0V, ±50 mV typical

　　Output Range: 0 to 10V

　　Output Noise:

　　0 to 10V Range: 14.95 μVrms typical

　　±10V Range: 31.67 μVrms typical

　　Settling Time (To 1 LSB Accuracy): 25 μS typical

　　Slew Rate:

　　0 to 10V Range: 1.20V/μS typical

　　±10V Range: 1.20V/μS typical

　　Throughput:

　　Single-Channel: 100 S/s maximum, system-dependent

　　Multichannel: 100 S/s/#ch maximum, system-dependent

　　ANALOG OUTPUT CALIBRATION

　　Recommended Warm-Up Time: 15 minutes minimum on-board precision reference

　　DC Level: 5.000V ±1 mV maximum

　　Tempco: ±10 ppm/°C maximum

　　Long-Term Stability: ±10 ppm/SQRT(1000 hrs)

　　Calibration Method: Software calibration

　　Calibration Interval: 1 year

　　DIGITAL I/O

　　Digital Logic Type: CMOS

　　Number of I/O: 8

　　Configuration: Independently-configured for input or output

　　Pull-Up/Pull-Down Configuration: Softwareable; all pins floating (default). For pull-down, connect the DIO CTL pin to a DGND pin. For pull-up, connect the DIO CTL pin to the 5V pin.

　　Digital I/O Input Loading: TTL (default); 47 KΩ (pull-up/pull down configurations)

　　Digital I/O Transfer Rate (System-Paced): System-dependent, 33 to 1000 port reads/writes or single bit reads/writes per second.

　　Input High Voltage: 2.0V minimum, 5.5V absolute maximum

　　Input Low Voltage: 0.8V maximum, -0.5V absolute minimum

　　Output High Voltage (IOH = -2.5 mA): 3.8V minimum

　　Output Low Voltage (IOL = 2.5 mA): 0.7V maximum

　　Power On and Reset State: Input

　　SYNCHRONOUS DAC LOAD

　　Pin Name: SYNCLD (terminal block pin 49)

　　Power On and Reset State: Input

　　Pin Type: Bidirectional

　　Termination: Internal 100 K pull-down

　　Software-able Direction:

　　Output: Outputs internal D/A LOAD signal

　　Input: Receives D/A LOAD signal from external source

　　Input Clock Rate: 100 Hz maximum

　　Clock Pulse Width:

　　Input: 1 μs minimum

　　Output: 5 μs minimum

　　Input Leakage Current: ±1.0 μA typ

　　Input High Voltage: 4.0V minimum, 5.5V absolute maximum

　　Input Low Voltage: 1.0V maximum, -0.5V absolute minimum

　　Output High Voltage:

　　IOH: -2.5 mA: 3.3V minimum

　　No Load: 3.8V minimum; SYNCLD is a Schmitt trigger input and is overcurrent protected with a 200 Ω series resistor

　　Output Low Voltage:

　　IOL: 2.5 mA: 1.1V maximum

　　No Load: 0.6V maximum; When SYNCLD is in input mode, the analog outputs may either be d immediately or when a positive edge is seen on the SYNCLD pin (this is under software control). However, the pin must be at a low logic level in order for the DAC outputs to be d immediately. If an external source is pulling the pin high, no occurs.

　　COUNTER

　　Pin Name: CTR

　　Number of Channels: 1

　　Resolution: 32-bits

　　Counter Type: Event counter

　　Input Type: TTL, rising edge triggered

　　Counter Read/Write Rates (Software-Paced): System dependent, 33 to 1000 reads per second

　　Schmidt Trigger Hysteresis: 20 to 100 mV

　　Input Leakage Current: ±1.0 μA typical

　　Input Frequency: 1 MHz maximum

　　High Pulse Width: 500 ns minimum

　　Low Pulse Width: 500 ns minimum

　　Input High Voltage: 4.0V minimum, 5.5V absolute maximum

　　Input Low Voltage: 1.0V maximum, -0.5V absolute minimum

　　MEMORY

　　EEPROM: 256 bytes

　　EEPROM Configurati

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